This invention relates generally to the field of die placement, and in particular, to improving accuracy during placement of die onto a flex substrate such as polyimide flex.
The technique of adaptive lithography for die placement involves measuring the misalignment of specified preexisting features (e.g. die bond pads or fiducial marks on prior metal layers), and modifying the routing of metal lines and vias to correspond to these misalignments. If one were using conventional lithography tools, this would be analogous to fabricating a custom mask for each layer of artwork exposed on each unique part. The employment of a virtual mask (i.e., a mask which is written directly from computer memory onto the parts), and the automated customization of the artwork, prevents this from being cost-prohibitive.
Yet, there are still drawbacks to this approach. It is capital-intensive, requiring custom equipment for automating the customization of the interconnect artwork to accommodate misalignment of die and distortion of prior layers of routing. It is also computationally intensive, as design rules for minimum line width and pitch must be followed while rerouting lines, and each artwork is unique to the part it represents. Finally, and most importantly, as currently practiced this procedure remains highly labor intensive. The precise measurement of misregistration of each die, and of the distortion of flexible substrates has not been fully automated. Techniques have been developed to generalize flex distortion and reduce the number of measurements, and custom xe2x80x9cComponent Mapping Systemsxe2x80x9d (CMS) can be used to reduce the number of man-hours required to acquire the data needed to accurately customize artwork for each unique part. But a significant amount of operator involvement is still required for setup, discretion (to supplement/override the automated vision system of the CMS), and tracking to ensure that the correct artwork is exposed on each corresponding part.
In one form of high density interconnect (HDI) circuit module, an adhesive-coated polymer film overlay is applied over a substrate which can support integrated circuit chips in chip wells. Via openings are then formed to expose chip pads of the integrated circuit chips. The polymer film provides an insulated layer upon which is deposited a metallization pattern for interconnection of substrate metallization and/or individual circuit chips through the vias. Methods for performing an HDI process using overlays are further described in Eichelberger et al., U.S. Pat. No. 4,783,695, and in Eichelberger et al., U.S. Pat. No. 4,933,042. Generally a plurality of polymer film overlays and metallization patterns are used.
In another form of circuit module fabrication (referred to herein as chip-on-flex), as described by commonly assigned Cole et al., U.S. Pat. No. 5,527,741, a method for fabricating a circuit module includes using a flexible interconnect layer having a metallized base insulative layer and an outer insulative layer. At least one circuit chip having chip pads is attached to the base insulative layer and vias are formed in the outer and base insulative layers to expose selected portions of the base insulative layer metallization and the chip pads. A substrate can be molded around the attached chip or chips. A patterned outer metallization layer is applied over the outer insulative layer extending through selected ones of the vias to interconnect selected ones of the chip pads and selected portions of the base insulative layer metallization.
In the standard chip-on-flex processes such as disclosed in aforementioned Cole et al., U.S. Pat. No. 5,527,741, the die are placed on flex substrate such as polyimide flex by interpolative alignment to xe2x80x9cglobalxe2x80x9d fiducials patterned in metal which are typically located at the outer extents of the module layout. The accuracy of die placement within 25xcexc of target has a Zst of 1.79"sgr" (see FIG. 6), wherein Zst is defined as the xe2x80x9cshort term sigma.xe2x80x9d Zst is a statistical measure of how often defects (i.e. die misplacements in this case) are likely to occur. The higher the sigma value, the less likely a process will produce defects. As a result of this, alignment of the flex metal interconnect through vias to the die bond pads is generally accomplished with the use of xe2x80x9cadaptive lithographyxe2x80x9d such as described in Eichelberger et al., U.S. Pat. No. 4,835,704. Adaptive lithography is a method which can accommodate die placement errors by creating xe2x80x9ccustomxe2x80x9d direct write artwork for the position of laser drilled vias and the subsequent interconnect metal patterning. Although this process works well, it requires custom built equipment which is expensive and relatively difficult to maintain. It also requires a very large data file to store unique artwork for each module processed. The resulting xe2x80x9cadaptivexe2x80x9d artwork also limits the design rules of the interconnect layout near die. This becomes increasingly more important as the size of die and die bond pads shrink. It is estimated that by the year 2007, the die bond pad size will shrink to 40xcexc on a 55xcexc pitch. Interconnect routing using adaptive lithography will become very difficult.
E. W. Balch et al., U.S. Pat. No. 6,284,564, discloses a process in which vias are pre-drilled through flex substrate coated with adhesive. The die are then aligned to the pre-drilled vias, and placed in the adhesive. This method depends heavily on the flow properties of the die attach adhesive. To provide void-free attachments, the optimum die attach adhesives for chip-on-flex flow during curing. With this method, adhesive also flows into the pre-drilled vias during the cure process, and can not be removed. If the via is not open, contact to the die bond pad can not be made. The pre-drilled vias in polyimide are also not an optimum structure for die placement alignment.
Further, avoiding sharp via corners is typically advantageous to improve reliability, reduce stress, and allow for more efficient interconnect routing designs.
Thus, it is desirable to provide an alternate method of aligning the die to the interconnect metal on the flex using commercially available equipment, while eliminating the use of adaptive lithography and expensive custom equipment. A benefit of this would be the ability to accommodate multi-chip module (MCM) interconnect routing necessary for the next generation die.
It is further desirable to provide a method of forming non-rectangular vias, allowing the via shape, determined by the metal pattern and the etching technique, to be varied. Round vias, for example, may improve reliability because they have no stress points, and may allow for more efficient interconnect routing designs.
It is further desirable to provide the ability to remove dielectric material from the surface of MMIC or MEMS die for improved electrical performance or mechanical function, in large areas, not just small vias.
It is further desirable to enable the formation of vias to bond pads using any of a variety of methods (e.g., RIE (reactive ion etching), plasma etching, excimer ablation).
Briefly, in accordance with one embodiment of the invention, a method for aligning die to interconnect metal on a flex substrate to produce at least one electronic chip package comprises patterning a mask for via formation in a via mask layer on a bottom surface of said flex substrate; and adaptively aligning at least one bond pad of at least one die to local fiducials of the via mask layer.
As a result of this process, the flex metal artwork does not have to be customized for each die misplacement using xe2x80x9cadaptive lithographyxe2x80x9d. Die are placed based on the local details of the interconnected artwork, rather than interconnect artwork being adapted to suit the prior placement of die. Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost. The method is compatible with the projected designs of the next generation die which will have bond pads on the order of 40 um in size.